DFI - Ddr-phy.org
AUSTIN, Texas, Might 2, 2018 - The DDR PHY Interface (DFI) Group today released version 5.Zero of the specification for interfaces between high-pace Memory Wave controllers and physical (PHY) interfaces to help the requirements of future cell and server memory standards. The DFI specs, broadly adopted all through the Memory Wave business, allow larger interoperability. The DFI Group included a number of interface enhancements in this latest specification. The new model of the specification adds protocol help for the most recent DDR and low-power memory applied sciences. Previous versions of the specification outlined memory coaching throughout the interface between the memory controller and the PHY. The new specification utterly transitions to PHY-impartial coaching mode where the PHY trains the memory interface without involving the controller. Other interface improvements embody lower energy enhancements, offering a PHY-independent boot sequence, increasing frequency change support, and defining new controller-to-PHY interface interactions. "The trade is starting to embrace new low-power and DDR memory applied sciences, together with excessive-performance gadgets corresponding to servers, storage, and networking; autonomous vehicles; and low-energy handheld units and IoT," said John MacLaren, DFI Group chairman and Cadence design engineering architect.
"The DFI Group, consisting of specialists from main firms within the trade, is enthusiastic to contribute to enabling this transition with the most recent launch of the DFI specification. "Adopting open and normal interfaces like the new DFI 5.Zero specification for prime-velocity Memory Wave App controller and PHY interface permits AMD to effectively and successfully undertake new memory requirements as we deliver high-performance products to our prospects. "Cadence has been a key contributor to the DFI 5.0 normal, which helps to make sure interoperability between DDR PHYs and DDR controllers, particularly for future memory units," mentioned Marc Greenberg, group director, product advertising and marketing, DDR, HBM, flash/storage and MIPI IP. "As a leading supplier of DDR IP and Verification IP, Synopsys makes vital investments to ensure that our DesignWare® controller and PHY IP are compliant to business standards comparable to DFI," said Navraj Nandra, Sr. Director of selling for Interface and Analog IP solutions at Synopsys.
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