Imec Proposes 3D Cost-coupled Gadget With IGZO Channel As Buffer Memory For Data-intensive Compute Functions
LEUVEN (Belgium), December 12, 2024- This week, at the 2024 IEEE International Electron Units Assembly (IEDM), imec, a world-main research and innovation hub in nanoelectronics and digital technologies, proposes a novel 3D built-in charge-coupled system (CCD) that may function as a block-addressable buffer memory, in help of information-intensive compute applications. Memory operation is demonstrated on a planar proof-of-idea CCD structure which may retailer 142 bits. Implementing an oxide semiconductor channel materials (comparable to IGZO) ensures sufficiently long retention time and allows 3D integration in a cost-efficient, 3D NAND-like structure. Imec expects the 3D CCD memory density to scale far beyond the DRAM restrict. The latest introduction of the compute specific hyperlink (CXL) memory interface gives opportunities for brand spanking new recollections to complement DRAM in information-intensive compute purposes like AI and ML. One example is the CXL sort-three buffer Memory Wave System, envisioned as an off-chip pool of recollections that ‘feeds’ the assorted processor cores with giant data blocks via a high-bandwidth CXL switch. This class of recollections meets completely different specs than byte-addressable DRAM, which increasingly struggles to maintain the fee-per-bit-development scaling line.
At IEDM 2024, imec proposes a cost-coupled system (CCD) with IGZO channel built-in right into a 3D NAND-Flash string structure as a promising candidate for CXL kind-3 buffer memory - to attain the required characteristics of block addressability, unlimited endurance, low fabrication value, and ample knowledge retention. As a first step in direction of real implementations, imec demonstrated memory operation of the CCD with IGZO on a 2D proof-of-idea. The planar CCD structure of this 2D proof-of-idea consists of an enter stage, 142 phases (each consisting of four part gates) which may every retailer one bit, and Memory Wave a two-transistor-based mostly learn-out stage. The CCD register is written by injecting fees via the enter stage and sequentially transferring them by all 142 levels by switching the voltages of the part gates. 1010 cycles with out degradation, and a cost switch speed exceeding 6MHz. Multilevel storage capability of the CCD register was also demonstrated, contributing to a better bit density. Being widely adopted in the image sensor market, the charge-based mostly CCD technology is effectively-recognized, reliable, and may function at low voltages - benefiting energy consumption. Maarten Rosmeulen, Memory Wave System Program Director Storage Memory at imec: "The real worth of the proposed buffer memory lies in its potential to be integrated into 3D NAND trend, with IGZO-based mostly CCD registers built-in into vertically aligned plugs - an idea that we now propose for the primary time.
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