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		<title>Memory Half 2: CPU Caches - Versionsgeschichte</title>
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		<updated>2026-04-23T14:30:15Z</updated>
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		<title>ErlindaRevell am 2. Oktober 2025 um 13:58 Uhr</title>
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				<updated>2025-10-02T13:58:50Z</updated>
		
		<summary type="html">&lt;p&gt;&lt;/p&gt;
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			&lt;td colspan='2' style=&quot;background-color: white; color:black;&quot;&gt;← Nächstältere Version&lt;/td&gt;
			&lt;td colspan='2' style=&quot;background-color: white; color:black;&quot;&gt;Version vom 2. Oktober 2025, 13:58 Uhr&lt;/td&gt;
			&lt;/tr&gt;&lt;tr&gt;&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Zeile 1:&lt;/td&gt;
&lt;td colspan=&quot;2&quot; class=&quot;diff-lineno&quot;&gt;Zeile 1:&lt;/td&gt;&lt;/tr&gt;
&lt;tr&gt;&lt;td class='diff-marker'&gt;−&lt;/td&gt;&lt;td style=&quot;background: #ffa; color:black; font-size: smaller;&quot;&gt;&lt;div&gt;&amp;lt;br&amp;gt;It &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;should &lt;/del&gt;have been &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;famous in &lt;/del&gt;the textual content that a lot of the description of multi-cache &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;interaction &lt;/del&gt;is &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;particular &lt;/del&gt;to x86 and &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;similarly &lt;/del&gt;&amp;quot;sequentially-&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;consistent&lt;/del&gt;&amp;quot; architectures. Most modern architectures &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;are &lt;/del&gt;not sequentially &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;consistent&lt;/del&gt;, and threaded &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;programs have to &lt;/del&gt;be &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;extremely &lt;/del&gt;careful about one thread &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;relying &lt;/del&gt;on &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;knowledge &lt;/del&gt;written by &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;another &lt;/del&gt;thread becoming visible within the order &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;by &lt;/del&gt;which it was written. Alpha, PPC, Itanium, and (&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;typically&lt;/del&gt;) SPARC, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;but &lt;/del&gt;not x86, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt; [https://gitea.mahss.io/caseykoontz992 Memory Wave] &lt;/del&gt;AMD, or MIPS. The consequence of the requirement to keep up sequential consistency is poor &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;performance &lt;/del&gt;and/or horrifyingly &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;complicated &lt;/del&gt;cache interaction &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;equipment &lt;/del&gt;on machines with greater than (about) 4 CPUs, so we &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;will anticipate &lt;/del&gt;to see extra non-x86 multi-core chips in use &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;quickly&lt;/del&gt;. I &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;think &lt;/del&gt;your criticism is misdirected. The &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;text &lt;/del&gt;would not &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;touch &lt;/del&gt;on memory consistency in any respect - it is &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;totally &lt;/del&gt;out of its scope. &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;Moreover&lt;/del&gt;, you &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;want &lt;/del&gt;a cache coherency protocol on any multi processor system. On the subject of memory consistency, there are &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;completely &lt;/del&gt;different opinions.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;Some time &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;ago &lt;/del&gt;there was a very &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;fascinating dialogue &lt;/del&gt;in RealWorldTech &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;where &lt;/del&gt;Linus Torvalds made an &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;fascinating &lt;/del&gt;point that it may be argued that &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;express &lt;/del&gt;memory &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;barriers &lt;/del&gt;are &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;dearer &lt;/del&gt;than what the CPU has to do &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;as a way &lt;/del&gt;to create the illusion of sequential memory consistency, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;because express MBs are by necessity extra common and &lt;/del&gt; [http://&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;www&lt;/del&gt;.&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;vokipedia.de&lt;/del&gt;/&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;index.php?title=Benutzer:GilbertoWillason MemoryWave&lt;/del&gt;] &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;even &lt;/del&gt;have stronger &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;guarantees&lt;/del&gt;. Sorry, not true. It describes how caches of various x86 CPUs &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;interact&lt;/del&gt;, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt; [https://foutadjallon.com/index.php/We_Hope_You_ll_Be_A_Part_Of_Us Memory Wave] however does &lt;/del&gt;not say it only describes x86, falsely suggesting that &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;is &lt;/del&gt;how &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;every &lt;/del&gt;different machine does it too. It leaves the reasonable reader &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;below &lt;/del&gt;the impression that programmers &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;don't &lt;/del&gt;need &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;to &lt;/del&gt;know anything about memory consistency. That&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;'s &lt;/del&gt;not &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;completely &lt;/del&gt;true even on x86, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;but &lt;/del&gt;is &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;just &lt;/del&gt;false on most non-x86 platforms. If Ulrich is writing for &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;individuals &lt;/del&gt;programming &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;solely &lt;/del&gt;x86, the article ought to say so with out quibbling. If not, it &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;ought to name &lt;/del&gt;out locations &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;the place &lt;/del&gt;it&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;'s &lt;/del&gt;describing x86-&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;particular habits&lt;/del&gt;. To the &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;better &lt;/del&gt;of my information, the &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;description &lt;/del&gt;in the article applies to all cache coherent techniques, together with &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;those &lt;/del&gt;listed in your earlier &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;submit&lt;/del&gt;.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;It has nothing to do with &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;memory &lt;/del&gt;consistency, which is an issue principally &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;inside &lt;/del&gt;to the CPU. I'm very &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;presumably fallacious&lt;/del&gt;, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;after all &lt;/del&gt;- I'm not a hardware system designer - so I'm glad to &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;discuss &lt;/del&gt;it. &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;Are &lt;/del&gt;you &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;able to &lt;/del&gt;describe how the cache/memory &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;conduct &lt;/del&gt;in an Alpha (for instance; or &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;every &lt;/del&gt;other weak consistency system) differs from the article ? I agree that coding with &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;memory boundaries &lt;/del&gt;(&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;etc&lt;/del&gt;.!) is a giant topic, and &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;past &lt;/del&gt;the scope of this installment. It could have sufficed, although, to &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;say &lt;/del&gt;that (and &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;the place&lt;/del&gt;) it is a matter for concern, and why. 86 and x86-&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;sixty four &lt;/del&gt;really aren't sequentially-&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;consistent&lt;/del&gt;, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;as a result of &lt;/del&gt;this &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;might &lt;/del&gt;lead to an enormous &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;performance &lt;/del&gt;hit. They implement &amp;quot;processor consistency&amp;quot; which &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;means masses &lt;/del&gt;can &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;cross shops &lt;/del&gt;but no different reordering is allowed (&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;aside from &lt;/del&gt;some &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;special &lt;/del&gt;instructions). Or to &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;put &lt;/del&gt;it &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;one other way&lt;/del&gt;, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;masses &lt;/del&gt;have an acquire barrier and &lt;del class=&quot;diffchange diffchange-inline&quot;&gt; [https://oerdigamers.info/index.php/User:Raquel3873 MemoryWave] &lt;/del&gt;stores have a launch barrier.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;Implementations can situation masses to the bus out of order, &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;but &lt;/del&gt;will invalidate early &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;hundreds &lt;/del&gt;if &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;necessary &lt;/del&gt;to &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;attain &lt;/del&gt;the &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;identical &lt;/del&gt;have an effect on as if all &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;loads had been finished &lt;/del&gt;so as. &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;Express &lt;/del&gt;memory barrier &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;instructions &lt;/del&gt;may be &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;essential &lt;/del&gt;or useful even on x86 and x86-64. &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;However &lt;/del&gt;ideally programmers will use portable locking or lockless abstractions as &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;an alternative&lt;/del&gt;. The &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;idea &lt;/del&gt;of disabling hyperthreading (SMT) within the BIOS as a manner to &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;reduce &lt;/del&gt;cache misses and presumably &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;increase &lt;/del&gt;efficiency is attention-grabbing (and pertinent to me as I run a system with such a CPU and motherboard). In &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;any case&lt;/del&gt;, my CPU &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;seems &lt;/del&gt;to &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;utilize &lt;/del&gt;this feature about 10% of the time, and even then it's &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;often &lt;/del&gt;(99.99% of the time) with two distinct, non-threaded &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;purposes&lt;/del&gt;. It does seem logical that, if the hyperthreaded CPU &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;shows &lt;/del&gt;as two CPUs to the OS (I get two penguins at boot time plus cat /proc/cpuinfo shows two processors), but each digital CPU is sharing the identical 512K of L2 cache, then &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;possibly &lt;/del&gt;my Laptop is sucking rocks in performance because of the cache miss &lt;del class=&quot;diffchange diffchange-inline&quot;&gt;price &lt;/del&gt;alone.&amp;lt;br&amp;gt;&lt;del class=&quot;diffchange diffchange-inline&quot;&gt;[https://www.reference.com/science-technology/wave-summation-62ebfc0be934b178?ad=dirN&amp;amp;qo=paaIndex&amp;amp;o=740005&amp;amp;origq=memory+wave reference.com]&lt;/del&gt;&lt;/div&gt;&lt;/td&gt;&lt;td class='diff-marker'&gt;+&lt;/td&gt;&lt;td style=&quot;background: #cfc; color:black; font-size: smaller;&quot;&gt;&lt;div&gt;&amp;lt;br&amp;gt;It &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;ought to &lt;/ins&gt;have been &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;noted within &lt;/ins&gt;the textual content that a lot of the description of multi-cache &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;interplay &lt;/ins&gt;is &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;specific &lt;/ins&gt;to x86 and &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;equally &lt;/ins&gt;&amp;quot;sequentially-&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;constant&lt;/ins&gt;&amp;quot; architectures. Most &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;[https://www.saaspegasus.com/guides/&lt;/ins&gt;modern&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;-javascript-for-django-developers/client-server-&lt;/ins&gt;architectures&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;/ modern architectures] will &lt;/ins&gt;not &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;be &lt;/ins&gt;sequentially &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;constant&lt;/ins&gt;, and threaded &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;packages should &lt;/ins&gt;be &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;extraordinarily &lt;/ins&gt;careful about one thread &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;depending &lt;/ins&gt;on &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;information &lt;/ins&gt;written by &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;one other &lt;/ins&gt;thread becoming visible within the order &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;in &lt;/ins&gt;which it was written. Alpha, PPC, Itanium, and (&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;sometimes&lt;/ins&gt;) SPARC, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;however &lt;/ins&gt;not x86, AMD, or MIPS. The consequence of the requirement to keep up sequential consistency is poor &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;efficiency &lt;/ins&gt;and/or horrifyingly &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;advanced &lt;/ins&gt;cache interaction &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;machinery &lt;/ins&gt;on machines with greater than (about) 4 CPUs, so we &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;are able to count on &lt;/ins&gt;to see extra non-x86 multi-core chips in use &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;soon&lt;/ins&gt;. I &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;feel &lt;/ins&gt;your criticism is misdirected. The &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;textual content &lt;/ins&gt;would not &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;contact &lt;/ins&gt;on memory consistency in any respect - it is &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;solely &lt;/ins&gt;out of its scope. &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;Besides&lt;/ins&gt;, you &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;need &lt;/ins&gt;a cache coherency protocol on any multi processor system. On the subject of memory consistency, there are different opinions.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;Some time &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;in the past &lt;/ins&gt;there was a very &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;attention-grabbing discussion &lt;/ins&gt;in RealWorldTech &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;the place &lt;/ins&gt;Linus Torvalds made an &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;interesting &lt;/ins&gt;point that it may be argued that &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;explicit &lt;/ins&gt;memory &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;limitations &lt;/ins&gt;are &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;more expensive &lt;/ins&gt;than what the CPU has to do &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;with the intention &lt;/ins&gt;to create the illusion of sequential memory consistency,&amp;#160; [http://&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;frp-old&lt;/ins&gt;.&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;com:41879&lt;/ins&gt;/&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;calvinkeynes63 Memory Wave&lt;/ins&gt;] &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;as a result of explicit MBs are by necessity extra basic and actually &lt;/ins&gt;have stronger &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;ensures&lt;/ins&gt;. Sorry, not true. It describes how caches of various x86 CPUs &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;work together&lt;/ins&gt;, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;but would &lt;/ins&gt;not say it only describes x86, falsely suggesting that&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;'s &lt;/ins&gt;how &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;each &lt;/ins&gt;different machine does it too. It leaves the reasonable reader &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;beneath &lt;/ins&gt;the impression that programmers need &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;not &lt;/ins&gt;know anything about memory consistency. That &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;is &lt;/ins&gt;not &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;fully &lt;/ins&gt;true even on x86, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;however &lt;/ins&gt;is &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;simply &lt;/ins&gt;false on most non-x86 platforms. If Ulrich is writing for &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;people &lt;/ins&gt;programming &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;only &lt;/ins&gt;x86, the article ought to say so with out quibbling. If not, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt; [https://wavedream.wiki/index.php/User:JennyGopinko Memory Wave App] &lt;/ins&gt;it &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;should call &lt;/ins&gt;out locations &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;where &lt;/ins&gt;it &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;is &lt;/ins&gt;describing x86-&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;specific conduct&lt;/ins&gt;. To the &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;best &lt;/ins&gt;of my information, the &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;outline &lt;/ins&gt;in the article applies to all cache coherent techniques, together with &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;the ones &lt;/ins&gt;listed in your earlier &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;post&lt;/ins&gt;.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;It has nothing to do with &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;[http://cloud4.co.kr/bbs/board.php?bo_table=data&amp;amp;wr_id=554249 Memory Wave] &lt;/ins&gt;consistency, which is an issue principally &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;inner &lt;/ins&gt;to the CPU. I'm very &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;possibly unsuitable&lt;/ins&gt;, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;of course &lt;/ins&gt;- I'm not a hardware system designer - so I'm glad to &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;debate &lt;/ins&gt;it. &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;Can &lt;/ins&gt;you describe how the cache/memory &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;behavior &lt;/ins&gt;in an Alpha (for instance; or &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;any &lt;/ins&gt;other weak consistency system) differs from the article ? I agree that coding with &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;[http://pasarinko.zeroweb.kr/bbs/board.php?bo_table=notice&amp;amp;wr_id=7077752 Memory Wave App] obstacles &lt;/ins&gt;(&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;and so on&lt;/ins&gt;.!) is a giant topic, and &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;beyond &lt;/ins&gt;the scope of this installment. It could have sufficed, although, to &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;mention &lt;/ins&gt;that (and &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;where&lt;/ins&gt;) it is a matter for concern, and why. 86 and x86-&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;64 &lt;/ins&gt;really aren't sequentially-&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;constant&lt;/ins&gt;, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;because &lt;/ins&gt;this &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;is able to &lt;/ins&gt;lead to an enormous &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;efficiency &lt;/ins&gt;hit. They implement &amp;quot;processor consistency&amp;quot; which &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;implies loads &lt;/ins&gt;can &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;pass stores &lt;/ins&gt;but no different reordering is allowed (&lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;except for &lt;/ins&gt;some &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;particular &lt;/ins&gt;instructions). Or to &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;place &lt;/ins&gt;it &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;another method&lt;/ins&gt;, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;hundreds &lt;/ins&gt;have an acquire barrier and stores have a launch barrier.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;Implementations can situation masses to the bus out of order, &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;however &lt;/ins&gt;will invalidate early &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;loads &lt;/ins&gt;if &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;needed &lt;/ins&gt;to &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;realize &lt;/ins&gt;the &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;same &lt;/ins&gt;have an effect on as if all &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;masses were executed &lt;/ins&gt;so as. &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;Explicit &lt;/ins&gt;memory barrier &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;directions &lt;/ins&gt;may be &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;vital &lt;/ins&gt;or useful even on x86 and x86-64. &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;But &lt;/ins&gt;ideally programmers will use portable locking or lockless abstractions as &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;a substitute&lt;/ins&gt;. The &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;concept &lt;/ins&gt;of disabling hyperthreading (SMT) within the BIOS as a manner to &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;cut back &lt;/ins&gt;cache misses and presumably &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;enhance &lt;/ins&gt;efficiency is attention-grabbing (and pertinent to me as I run a system with such a CPU and motherboard). In &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;spite of everything&lt;/ins&gt;, my CPU &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;appears &lt;/ins&gt;to &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;make the most of &lt;/ins&gt;this feature about 10% of the time, and even then it's &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;usually &lt;/ins&gt;(99.99% of the time) with two distinct, non-threaded &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;functions&lt;/ins&gt;. It does seem logical that, if the hyperthreaded CPU &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;exhibits &lt;/ins&gt;as two CPUs to the OS (I get two penguins at boot time plus cat /proc/cpuinfo shows two processors), but each digital CPU is sharing the identical 512K of L2 cache, then &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;perhaps &lt;/ins&gt;my Laptop is sucking rocks in performance because of the cache miss &lt;ins class=&quot;diffchange diffchange-inline&quot;&gt;rate &lt;/ins&gt;alone.&amp;lt;br&amp;gt;&lt;/div&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/table&gt;</summary>
		<author><name>ErlindaRevell</name></author>	</entry>

	<entry>
		<id>http://www.vokipedia.de/index.php?title=Memory_Half_2:_CPU_Caches&amp;diff=93237&amp;oldid=prev</id>
		<title>GilbertoWillason: Die Seite wurde neu angelegt: „&lt;br&gt;It should have been famous in the textual content that a lot of the description of multi-cache interaction is particular to x86 and similarly &quot;sequentially…“</title>
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				<updated>2025-08-09T18:23:24Z</updated>
		
		<summary type="html">&lt;p&gt;Die Seite wurde neu angelegt: „&amp;lt;br&amp;gt;It should have been famous in the textual content that a lot of the description of multi-cache interaction is particular to x86 and similarly &amp;quot;sequentially…“&lt;/p&gt;
&lt;p&gt;&lt;b&gt;Neue Seite&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;lt;br&amp;gt;It should have been famous in the textual content that a lot of the description of multi-cache interaction is particular to x86 and similarly &amp;quot;sequentially-consistent&amp;quot; architectures. Most modern architectures are not sequentially consistent, and threaded programs have to be extremely careful about one thread relying on knowledge written by another thread becoming visible within the order by which it was written. Alpha, PPC, Itanium, and (typically) SPARC, but not x86,  [https://gitea.mahss.io/caseykoontz992 Memory Wave] AMD, or MIPS. The consequence of the requirement to keep up sequential consistency is poor performance and/or horrifyingly complicated cache interaction equipment on machines with greater than (about) 4 CPUs, so we will anticipate to see extra non-x86 multi-core chips in use quickly. I think your criticism is misdirected. The text would not touch on memory consistency in any respect - it is totally out of its scope. Moreover, you want a cache coherency protocol on any multi processor system. On the subject of memory consistency, there are completely different opinions.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;Some time ago there was a very fascinating dialogue in RealWorldTech where Linus Torvalds made an fascinating point that it may be argued that express memory barriers are dearer than what the CPU has to do as a way to create the illusion of sequential memory consistency, because express MBs are by necessity extra common and  [http://www.vokipedia.de/index.php?title=Benutzer:GilbertoWillason MemoryWave] even have stronger guarantees. Sorry, not true. It describes how caches of various x86 CPUs interact,  [https://foutadjallon.com/index.php/We_Hope_You_ll_Be_A_Part_Of_Us Memory Wave] however does not say it only describes x86, falsely suggesting that is how every different machine does it too. It leaves the reasonable reader below the impression that programmers don't need to know anything about memory consistency. That's not completely true even on x86, but is just false on most non-x86 platforms. If Ulrich is writing for individuals programming solely x86, the article ought to say so with out quibbling. If not, it ought to name out locations the place it's describing x86-particular habits. To the better of my information, the description in the article applies to all cache coherent techniques, together with those listed in your earlier submit.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;It has nothing to do with memory consistency, which is an issue principally inside to the CPU. I'm very presumably fallacious, after all - I'm not a hardware system designer - so I'm glad to discuss it. Are you able to describe how the cache/memory conduct in an Alpha (for instance; or every other weak consistency system) differs from the article ? I agree that coding with memory boundaries (etc.!) is a giant topic, and past the scope of this installment. It could have sufficed, although, to say that (and the place) it is a matter for concern, and why. 86 and x86-sixty four really aren't sequentially-consistent, as a result of this might lead to an enormous performance hit. They implement &amp;quot;processor consistency&amp;quot; which means masses can cross shops but no different reordering is allowed (aside from some special instructions). Or to put it one other way, masses have an acquire barrier and  [https://oerdigamers.info/index.php/User:Raquel3873 MemoryWave] stores have a launch barrier.&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;&amp;lt;br&amp;gt;Implementations can situation masses to the bus out of order, but will invalidate early hundreds if necessary to attain the identical have an effect on as if all loads had been finished so as. Express memory barrier instructions may be essential or useful even on x86 and x86-64. However ideally programmers will use portable locking or lockless abstractions as an alternative. The idea of disabling hyperthreading (SMT) within the BIOS as a manner to reduce cache misses and presumably increase efficiency is attention-grabbing (and pertinent to me as I run a system with such a CPU and motherboard). In any case, my CPU seems to utilize this feature about 10% of the time, and even then it's often (99.99% of the time) with two distinct, non-threaded purposes. It does seem logical that, if the hyperthreaded CPU shows as two CPUs to the OS (I get two penguins at boot time plus cat /proc/cpuinfo shows two processors), but each digital CPU is sharing the identical 512K of L2 cache, then possibly my Laptop is sucking rocks in performance because of the cache miss price alone.&amp;lt;br&amp;gt;[https://www.reference.com/science-technology/wave-summation-62ebfc0be934b178?ad=dirN&amp;amp;qo=paaIndex&amp;amp;o=740005&amp;amp;origq=memory+wave reference.com]&lt;/div&gt;</summary>
		<author><name>GilbertoWillason</name></author>	</entry>

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